1. Field of the Invention
The present invention relates to a semiconductor memory device capable of changing the number of memory sets.
2. Description of Related Art
FIG. 8 is a block diagram showing a conventional semiconductor memory device. In the figure, the reference numerals 1 to 6 designate memory cell arrays; and the reference numerals 7 to 12 designate read/write circuits connected to the memory cell arrays 1 to 6, respectively, which perform read/write of data for the memory cell arrays. Each read/write circuit 7 to 12 is composed of a write driver for writing data and a sense amplifier for reading data.
The reference numerals 13 and 14 designate address setting circuits which set an address and output a timing signal for reading/writing of the read/write circuits 7 to 9 and 10 to 12. Each address setting circuit 13 and 14 is composed of an address predecoder for setting an address in response to an address signal and outputting an address predecoding signal, an address buffer for storing the set address and a timing generator for outputting a timing signal according to a control signal.
The reference numerals 15 and 16 designate data buses and the reference numerals 17 and 18 designate data input/output buffers which hold data to be written into the memory cell arrays 1 to 3 and 4 to 6 or data read therefrom.
Next, the operation of the conventional semiconductor memory device will be described.
In the semiconductor memory device of FIG. 8, the number of independently operating memory sets in the same chip is two and cannot be changed. In other words, the memory cell arrays 1 to 3 constitute a first memory set, whereas the memory cell arrays 4 to 6 constitute the second memory set.
Thus, two xe2x80x9c3 Mbit 12IO memoryxe2x80x9d sets are provided in the semiconductor memory device of FIG. 8.
Although the number of independently operating memory sets in the same chip is fixed to two in the above-mentioned semiconductor memory device, the number of seemingly independently operating memory sets can be changed in a semiconductor memory device as shown in FIG. 9.
In the semiconductor memory device of FIG. 9, the same number of address setting circuits as that of memory cell arrays are provided so that each of t he memory cell arrays can independently operate.
In the conventional semiconductor memory device thus constructed, if address setting circuits whose number is the same as that of memory cell arrays are provided, the number of seemingly independently operating memory sets can be changed. However, the number of mounted address setting circuits increases compared with a case where the number of memory sets is fixed, resulting in an increase in the layout area of a semiconductor memory device.
The present invention is implemented to solve the above problems in the conventional semiconductor memory device. An object of the present invention is to provide a semiconductor memory device capable of changing the number of memory sets which seemingly independently operate without providing the same number of address setting circuits as that of memory cell arrays.
According to the present invention, there is provided a semiconductor memory device comprising; a plurality of memory cell arrays constituting a plurality of memory sets; a plurality read/write circuits, connected to the memory cell arrays, respectively, for performing read/write of data for the memory cell arrays; a plurality of address setting circuits for setting an address for reading/writing of the read/write circuits, a number of the address setting circuits being a maximum number of the memory sets; and switching means for switching a correspondence relationship between the memory cell arrays and the address setting circuits in response to a signal selecting a number of memory sets.
Here, the semiconductor memory device may further comprise; a data input/output buffer for holding data; and a data bus controller for controlling a connection relationship between a plurality of data buses connecting the read/write circuits to the data input/output buffer.
At a time of switching the correspondence relationship between the memory cell arrays and the address setting circuits, the switching means may disconnect a part of the memory cell arrays from a address setting circuit, if a required memory capacity can be obtained without activating all the memory cell arrays.
If a defect occurs in a memory cell array in use, the switching means may disconnect the defective memory cell array from an address setting circuit and connect another memory cell array which has been disconnected from the address setting circuit to the address setting circuit.
At a time of switching the correspondence relationship between the memory cell arrays and the address setting circuits, the switching means can change a capacity of each of the memory sets composed of at least one memory cell array.
The semiconductor memory device may further comprise a special pad pin for inputting the signal selecting the number of memory sets from an outside.
The semiconductor memory device may further comprise a special pad for inputting the signal selecting the number of memory sets, the pad being connected to a power supply or ground at a time of bonding.
The semiconductor memory device may further comprise a signal wiring for inputting the signal selecting the number of memory sets, the signal wiring being connected to a power supply or ground in a wafer process.
As stated above, according to the present invention, a semiconductor memory device is constructed so as to comprise switching means for switching a correspondence relationship between memory cell arrays and address setting circuits in response to a signal selecting a number of memory sets. Thus, the number of the memory sets which seemingly independently operate without providing the same number of address setting circuits as that of memory cell arrays.
According to the present invention, a semiconductor memory device is constructed so as to further comprise a data bus controller for controlling a connection relationship between a plurality of data buses connecting read/write circuits to a data input/output buffer. Thus, the IO number for use can be changed.
According to the present invention, a semiconductor memory device is constructed such that at a time of switching the correspondence relationship between memory cell arrays and address setting circuits, switching means can disconnect a part of the memory cell arrays from a address setting circuit, if a required memory capacity can be obtained without activating all the memory cell arrays. Thus, power consumption can be reduced.
According to the present invention, a semiconductor memory device is constructed such that if a defect occurs in a memory cell array in use, switching means disconnects the defective memory cell array from an address setting circuit and connects another memory cell array which has been disconnected from the address setting circuit to the address setting circuit. Thus, the yield of the semiconductor memory device can be increased.
According to the present invention, a semiconductor memory device is constructed such that at a time of switching the correspondence relationship between memory cell arrays and address setting circuits, switching means can change a capacity of each of memory sets composed of at least one memory cell array. Thus, the semiconductor memory device can be widely used for various applications.
According to the present invention, a semiconductor memory device is constructed so as to further comprise a special pad pin for inputting the signal selecting the number of memory sets from an outside. Thus, the semiconductor memory device can be used in a plurality of ways.
According to the present invention, a semiconductor memory device is constructed so as to further comprise a special pad for inputting the signal selecting the number of memory sets, the pad being connected to a power supply or ground at a time of bonding. Thus, cost savings can be realized.
According to the present invention, a semiconductor memory device is constructed so as to further comprise a signal wiring for inputting the signal selecting the number of memory sets, the signal wiring being connected to a power supply or ground in a wafer process. Thus, the later processes can be simplified.